Gbe Rgmii Receive Path Clock Routing Guidelines - Intel EP80579 Manual

Gigabit Ethernet (GbE) Interface—Intel
Table 85.

GbE RGMII Receive Path Clock Routing Guidelines

Routing Layer
Reference Plane
Board Trace Impedance
Trace Width
Clock Spacing (e2e)
PHY Clock Rx Breakout Length
(LClk_Brk_out_rx)
Clock Rx Board Length
(LClk_Brd_route_rx)
EP80579 Clock Tx Breakin Length
(LClk_Brk_in_rx)
Total Tx Clock Routing (LClk_total_rx)
Pull Up Resistor T-Line (Lpull_up)
Pull Up Resistor (Rpull_up)
Breakout\Breakin Spacing (e2e)
19.6.2.2 GbE Receive Data\Control Topology
The receive signals included in the GbE receive Data and Control topology
are:
— GBEn_RXCTL
— GBEn_RXDATA[3:0]
All the receive path Data and Control signals in a channel (see
length matched, routed on the same layer, and referenced to the Receive Clock in
section Section
channels, only within a channel.
Interface signals.
®
Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
Parameter
19.6.2.1. The signals do not need to be length matched between
Table 86
Routing Constraints
Stripline
Ground Reference
50 Ω
4.5mils (L3/L8)
20 mils (min)
0.5 inch (max)
min =1.0 inch
max = 7.0 inch
0.3 inch (max)
min =1.0 inch
max = 7.8 inch
0.625 inch (max)
1.2 KΩ (5%)
4 mils (min)
provides routing guidelines for the Receive
Microstrip
50 Ω
5.5mils (L1/L10)
25 mils (min)
0.5 inch (max)
min =1.0 inch
max = 7.0 inch
0.3 inch (max)
min =1.0 inch
max = 7.8 inch
0.625 inch (max)
1.2 KΩ (5%)
4 mils (min)
(Figure 141)
Figure 141) should be
May 2010
224