®
Contents-Intel
EP80579 Integrated Processor Product Line
7.1.5
7.2
7.2.1
Powergood Interface..............................................................................................86
7.2.2
Reset Interface ......................................................................................................86
7.2.3
Reset Sequence ....................................................................................................87
7.3
Power Management............................................................................................................88
7.3.1
Supported Power States ........................................................................................88
7.4
Power Sequencing..............................................................................................................90
8.0
Platform System Clock ..................................................................................................................91
8.1
8.2
System Clock Groups .........................................................................................................94
8.2.1
HOST_CLK Group .................................................................................................94
8.2.2
8.2.3
CLK33 Group .........................................................................................................99
8.2.4
CLK14 Group .......................................................................................................101
8.2.5
CLK48 Group .......................................................................................................102
8.3
8.3.1
8.3.2
Clock Power Delivery...........................................................................................104
8.3.3
8.3.4
8.3.5
IREF.....................................................................................................................110
8.3.6
EMI Constraints ...................................................................................................110
9.0
9.1
9.2
Supported Configurations .................................................................................................111
9.3
9.3.1
9.3.2
DRAM Addressing ...............................................................................................114
9.3.3
9.4
9.5
9.6
9.7
9.7.1
9.7.2
Reset Pin Requirement........................................................................................131
9.7.3
DC Bias Signals ...................................................................................................131
9.8
10.0 PCI Express* Interface ................................................................................................................135
10.1
10.1.4 Via Requirements ................................................................................................139
May 2010
Order Number: 320068-005US
®
Intel
EP80579 Integrated Processor Product Line
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