Intel EP80579 Manual page 272

Table 97. Layout Checklist (Sheet 4 of 13)
Signal Name
DDR_CK[5:0],
DDR_CK[5:0]#
DDR_CRES[0],
DDR_SLWCRES,
DDR_DRVCRES
DDR_RCOMPX
DDR_CRES[1],
DDR_CRES[2]
PEA0_Tp[7:0],
PEA0_Tn[7:0]
®
Intel EP80579 Integrated Processor Product Line
Platform Design Guide
272
®
Intel EP80579 Integrated Processor Product Line—Layout Checklist
Trace Geometry and
Impedance
Zo = 40 Ω +/- 10% single ended
Trace Width:
Brakeout Trace Width 4 mils
Stripline: 6.5 mils(L3/L8)
Airgap Spacing:
Brakeout spacing Min=4mils
DDR_CK to DDR_CK# 6mils
Pair to Pair Min=15mils
To any other signals Min=20mils
Trace Width:
Brakeout Trace Width 4 mils
Other routing 20 mils
Airgap Spacing:
Brakeout spacing Min=4mils
To any other signals Min=12mils
Trace Width:
Brakeout Trace Width 4 mils
Other routing 20 mils
Airgap Spacing:
Brakeout spacing Min=4mils
To any other signals Min=12mils
PCI Express Interface
Ω
Zdiff = 90 +/- 10%
Trace Width:
Brakeout Trace Width 4 mils
Microstrip: 4.75 mils
Stripline: 4.5 mils (L3/L8)
Airgap Spacing:
Brakeout spacing Min=4mils
Microstrip: 5.25 mils
Stripline: 5.5 mils
Spacing between Pairs, the
greater of the two
Microstrip: 20 mils or 3X
dielectric thickness.
Stripline: 18 mils or 3X dielectric
thickness.
Length Requirements
See
EP80579 to First DIMM
System
2.0 in to 4.0 in Max
Topology Point to Point
Groups are defined as follow:
Total Trace Length (TTL)
First group CLK/CLK#[2:0]
2.0 in - 6.0 in
Second group CLK/CLK#[5:3]
Reference Plane:
DDR_CK to DDR_CK#
Ground and Power reference
Match within 10 mils
plane.
Skew: Match all pair to
Route Clock group on the same
pair group within 20 mils.
layer from EP80579 to the
The shortest pair of the
farthest DIMM.
group must not exceed
No vias, except were required to
the longest pair of the
breakout.
group by 20 mils. This
requirement is for the
complete length from
EP80579 to the farthest
DIMM connector.
DDR_CK/DDR_CK# Clock
pairs should be match in
length to CMD/ADDR
within 20 mils
Total Trace Length (TTL)
Max=500mils
Keep traces as short as possible.
Total Trace Length (TTL)
Max=500mils
Keep traces as short as possible.
Place the RC circuit as close as
possible to EP80579.
See
Inter-pair length
– EP80579 to PCI Express
matching: +/-5 mils.
Connector".
Within a link, the lane-to-
Interface System Interconnect.
lane skew should meet
the PCIe transmit skew
Maximum number of vias per
(tx-skew) specification.
signal is 4.
Comments
Section 9.7, "DDR2 Interface
Interconnect".
Section 10.1.7, "Topology 1
May 2010
Order Number: 320068-005US