Intel EP80579 Manual page 255

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Sideband Signals—Intel EP80579 Integrated Processor Product Line
Table 92. Sideband Signals (Sheet 2 of 4)
Signal Name
NMI
SMI_OUT#
STPCLK_OUT#
®
Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
Group
Non-Maskable Interrupt:
• NMI forces a non-maskable interrupt to the IA-32
CPU Sideband Output
• This signal should be pulled-down to GND using
System Management Interrupt:
• This EP80579 output signal is made visible to the
CPU Sideband Output
• Pull-up to EP80579 3.3V (VCC33) power supply
Note:
• This signal can be left as a no connect (NC) if not
Stop Clock Request:
• This EP80579 output signal is made visible to the
CPU Sideband Output
• Pull-up to EP80579 3.3V (VCC33) power supply
Note:
• This signal can be left as a no connect (NC) if not
Description
core CPU if configured. The CPU detects an NMI as
a rising edge on NMI. NMI is reset by setting the
corresponding NMI source enable/disable bit in the
NMI Status and Control Register (I/O Register 61h),
except when an external platform agent is driving
the NMI pin.
10KΩ ± 5% resistor.
platform for debug purposes only. This internal
EP80579 signal is active low output synchronous to
PCICLK that is asserted in response to one of many
enabled hardware or software events. On accepting
a System Management Interrupt, the processor
saves the current state and enter System
Management mode (SMM). An SMI Acknowledge
transaction is issued, and the processor begins
program execution from the SMM handler.
using 10KΩ ± 5% resistor if used.
used.
platform for debug purposes only. This internal
EP80579 signal is an active-low output synchronous
to PCICLK that is asserted in response to one of
many hardware or software events. When the
processor samples STPCLK_OUT# asserted, it
causes the processor to enter a low power Stop-
Grant state. The processor issues a Stop-Grant
Acknowledge transaction, and stops providing
internal clock signals to all processor core units
except the CPU FSB and CPU APIC units. The
processor continues to snoop bus transactions and
service interrupts while in Stop-Grant state. When
STPCLK_OUT# is deasserted, the processor restarts
its internal clock to all units and resumes execution.
The assertion of STPCLK_OUT# has no effect on the
bus clock; STPCLK_OUT# is an asynchronous CPU
input generated by the EP80579 IICH.
using 10KΩ ± 5% resistor if used.
used.
May 2010
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