Intel EP80579 Manual page 285

Table 100. Schematic Checklist (Sheet 2 of 26)
Checklist Items
NMI
SMI_OUT#
STPCLK_OUT#
RCIN#
A20GATE
CPURST#
CPUPWRGD_OUT
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Intel EP80579 Integrated Processor Product Line
Platform Design Guide
285
®
Intel EP80579 Integrated Processor Product Line—Schematics Checklist
I/O Type
Recommendations
(Default)
• Terminate to GND using 10KΩ
I/O
± 5% resistor if used.
• Pull up signal to Platform 3.3V
O (VCC3) using a 10KΩ ± 5%
resistor if used
• Can monitor signal using an
LED
O
• Pull up signal to Platform 3.3V
(VCC3) using a 10KΩ ± 5%
resistor if used
• Connect to Keyboard Reset
(KBDRST#) pin of the Keyboard
Controller provided by the
Super I/O device.
I
• Pull up signal to Platform 3.3V
(VCC3) using a 10KΩ ± 5%
resistor.
• Connect to A20M pin of the
Keyboard Controller provided
by the Super I/O device.
I
• Pull up signal to Platform 3.3V
(VCC3) power supply using
10KΩ ± 5% resistor
• Processor reset output signal
that can be used by a debug
tool.
O
• Pull up signal to Platform 3.3V
(VCC3) using a 10KΩ ± 5%
resistor if used
• Processor Internal Power Good
output signal that can be used
by a debug tool.
O (OD)
• Pull up signal to EP80579 3.3V
(VCC33) using a 10KΩ ± 5%
resistor .
Comments
Note:
• This signal should be pulled-down to
GND with a 10KΩ resistor if not
used
Note:
• This signal can be left as a no
connect (NC) if not used.
• This signal can be exposed via a
testpoint for debug purposes if not
used.
Note:
• This signal can be left as a no
connect (NC) if not used.
• This signal can be exposed via a
testpoint for debug purposes if not
used.
Note:
• This signal should be pull-up to 3.3V
with a 10KΩ resistor if not used
• Provides an alternative method to
assert A20M#.
Note:
• This signal should be pull-up to 3.3V
with a 10KΩ resistor if not used.
• Processor Bus Reset: The IMCH
asserts CPURST# while RSTIN# is
asserted and for approximately 1ms
after RSTIN# is deasserted. The
CPURST# allows the processor to
begin execution in a known state.
Note:
• This signal can be left as a no
connect (NC) if not used.
• This signal can be exposed via a
testpoint for debug purposes if not
used.
• CPU Power Good: This EP80579
output signal is made visible to the
platform for debug purposes only.
This signal is an open drain signal,
and requires an external pull-up
resistor. CPUPWRGD monitors an
internal signal connected directly
form the IICH to the processor and
represents a logical AND of PWROK
and VRMPWRGD signals.
Note:
• Pull up signal to EP80579 3.3V
(VCC33) using a 10KΩ ± 5% resistor
if not used.
• This signal can be exposed via a
testpoint for debug purposes if not
used.
Order Number: 320068-005US
May 2010