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Table 76.
Development Board GPIO Usage (Sheet 2 of 2)
Pin Name
GP18_IRQ36
GP19_IRQ37
GP20_IRQ26
GP21_IRQ27
GP23_IRQ28
GP24_IRQ29
GP25_IRQ38
GP26_SATA0GP
GP27_IRQ39
GP28_IRQ30
GP29_SATA1GP
GP30_IRQ31
GP31_IRQ32
GP33_IRQ33
GP34_IRQ34
GP40_IRQ35
LDRQ[1]_N
GPIO[48]
17.2
Interrupts
EP80579 provides support for up to four PCI interrupt pins (PIRQ[E:H]) and PCI 2.3
message-based interrupts. EP80579 also maintains support for ISA (legacy)-style
interrupts via the serial interrupt protocol (SERIRQ). PCI Interrupts (PIRQ[A:D]) are
not pinned out on EP80579, but supported via SERIRQ. When IOAPIC is active,
IRQ[39:24] are externally driven interrupts through GPIO pins, enabled if SIU_TXD2 is
pulled low on power-up.
Table 77
shows the mapping of the various interrupts when the IOAPIC is active.
Table 77.
Interrupt Configurations - APIC Mode (Sheet 1 of 2)
IRQ #
16
17
18
19
20
21
22
23
24
®
Intel
EP80579 Integrated Processor Product Line
Platform Design Guide
204
®
EP80579 Integrated Processor Product Line—General Purpose I/O (GPIO) and Interrupt
I/O
(Default
Mode)
I
T_GPO18_HSS2_INT_N
I
T_GPO19_HSS1_INT_N
O
T_GPO20_SMB_C
O
T_GPO21_SMB_B
O
T_GPO23_SMB_A
I/O
T_GPIO24_FPGA_IO_0
I/O
T_GPIO25_FPGA_IO_1
I
T_GPIO_26_FPGA_IN_11
I/O
T_GPIO27_FPGA_IO_2
I/O
T_GPIO28_FPGA_IO_3
I
T_GPIO_29_FPGA_IN_8
I
IMCH_SLP_N
I
T_GPI31
I/O
T_GPIO33_FPGA_IO_4
I/O
HPI_GPIO_34
I
IERR_GPI40
I
L_DRQ1_N
O
T_GPO_48_FPGA_OUT_5
Interrupt
Source
Name
PIRQA
SERIRQ
PIRQB
SERIRQ
PIRQC
SERIRQ
PIRQD
SERIRQ
PIRQE
External
PIRQF
External
PIRQG
External
PIRQH
External
External
Mode of
Signal Name
Operatio
n
IRQ36
IRQ37
GPO
GPO
GPO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
IRQ31
GPI
GPIO
GPIO
GPI
GPI
GPO
Pin Name
N/A
N/A
N/A
N/A
PIRQE
PIRQF
PIRQG
PIRQH
GPIO[16]
Interface
Function
HSS2_INT_N
HSS1_INT_N
SMBus_C Enable
SMBus_B Enable
SMBus_A Enable
FPGA_I/O_0
FPGA_I/O_1
FPGA_IN_11
FPGA_I/O_2
FPGA_I/O_3
FPGA_IN_8
Sleep signal by External Jumper
Header
FPGA_I/O_4/SPI Boot Select
HSS1 EXT
IERR Signal)
LPC DMA Request
FPGA_OUT_5
May 2010
Order Number: 320068-005US
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