Iref; Emi Constraints; Decoupling Capacitors Placement And Connectivity - Intel EP80579 Manual

Platform System Clock—Intel
Figure 70.

Decoupling Capacitors Placement and Connectivity

Decoupling
Caps
VDD_48
8.3.5

IREF

The IREF pin on the CK410 is connected to ground through a 475 Ω ±1% resistor,
making the IREF 2.32 mA.
8.3.6

EMI Constraints

Clocks are a significant contributor to EMI. The following recommendations can aid in
EMI reduction:
• Maintain uniform spacing between the two signals of each differential clock pair.
• Route clocks on physical layer adjacent to the VSS reference plane only.
• Use pull-down resistors to pull-down the unused clock signals to ground plane. This
prevents signals floating.
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Intel EP80579 Integrated Processor Product Line
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EP80579 Integrated Processor Product Line
VDD_A
Decoupling
Caps
May 2010
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