Gbe Rgmii Receive Path Data/Clock/Control Topology - Intel EP80579 Manual

Figure 141. GbE RGMII Receive Path Data/Clock/Control Topology
RGMII Receive Path Data\Control Topology
L
Pull_up
Pull Up
TL (μs)
EP80579
Via
Receiver
(Data\Ctrl)
LD\C_Total_rx =
NOTE: Breakout\ Breakin descriptions are as follows:
1. Routing where trace is 3.75 mil wide and 4mil spacing is implemented to escape\ enter BGA
2. The Breakout \ Breakin Length is defined from the pin of the BGA, to where 4 mil spacing
increases to the required spacing per SI recommendations.
a). Data\Ctrl = 12 mil edge-to-edge (e2e) for Stripline
b). Data\Ctrl = 18 mil edge-to-edge (e2e) for Microstrip
®
Intel EP80579 Integrated Processor Product Line
Platform Design Guide
225
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Intel EP80579 Integrated Processor Product Line—Gigabit Ethernet (GbE) Interface
(EP80579
V2P5
Rpull up
Break in Board
LD/C_Brk_in_rx LD\C_Brd_route_rx
LD\C_Brk_out_rx + LD\C_Brd_route_rx +
PHY)
PHY
Break out
Via
Transmitter
(Data\Ctrl)
LD\C_Brk_out_rx
LD\C_Brk_in_rx
Order Number: 320068-005US
May 2010