Supported Dram Capacity For 64-Bit Mode; Supported Dram Capacity For 32-Bit Mode - Intel EP80579 Manual

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System Memory Interface (DIMM)—Intel
Table 28
in the 64b mode. The first column shows the total DRAM capacity on the channel. The
remaining columns indicate the DRAM devices features, densities and the number of
devices required to achieve the given capacity. A single-sided DIMM is indicated by 0
parts populated on side B. A double-sided DIMM has parts populated on both sides.
For each configuration, an additional DRAM part per side is required to support ECC
bits. A x8 part provides all the bits required for ECC.
In the 64b configuration, the minimum capacity supported by the memory controller is
256 MB and the maximum capacity supported is 4 GB.
Table 28.

Supported DRAM Capacity for 64-bit Mode

Total DRAM
Capacity
256 MB
512 MB
1 GB
2 GB
4 GB
Table 29
32b mode.In the 32-bit mode only single rank DDR2 devices are supported. In this
mode, the minimum capacity supported by the memory controller is 128 MB and the
maximum capacity supported is 1 GB.
Table 29.

Supported DRAM Capacity for 32-bit Mode

Total DRAM
Capacity
128 MB
256 MB
512 MB
1GB
Note:
In the 32b mode, all unused EP80579 DDR2 Data Bus Interface signals should be
pulled high to DDR2 1.8V through 10 Kohm resistors.
Table 30
Dual DIMM support uses 2N or 2T command/address timing.
®
Intel
EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
shows the various capacity configurations supported by the memory controller
DRAM Technology
DRAM Part
DRAM Part
Density
Width
256 Mb
x8
256 Mb
x8
512 Mb
x8
512 Mb
x8
1 Gb
x8
1 Gb
x8
2 Gb
x8
2 Gb
x8
shows the various configurations supported by the memory controller in the
DRAM Technology
DRAM
DRAM Part
Density
Width
256 Mb
x8
512 Mb
x8
1 Gb
x8
2 Gb
x8
shows the supported DDR2 device speed grades for single and Dual DIMMs.
Total # of Parts
Total # of Parts
on Side A
on Side B
(without ECC)
(without ECC)
8
8
8
8
8
8
8
8
Total # of Parts on
Total # of Parts on
Side A
(without ECC)
(without ECC)
4
4
4
4
0
8
0
8
0
8
0
8
Side B
0
0
0
0
May 2010
112

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