Intel EP80579 Manual page 303

Table 100. Schematic Checklist (Sheet 20 of 26)
Checklist Items
GBE_REFCLK_RMII
GBE_RCOMPP
GBE_RCOMPN
MDC
MDIO
EEDO
EEDI
EECS
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Intel EP80579 Integrated Processor Product Line
Platform Design Guide
303
®
Intel EP80579 Integrated Processor Product Line—Schematics Checklist
I/O Type
Recommendations
(Default)
RGMII Mode
• Not used in this mode
I
• Connect through a 100Ω ±1%
resistor to Ground.
Note:
• Pull-down RMII Reference CLock (RMII) signal to GND using 100Ω resistor when the port
is not used in either mode.
• See Section 2.3
I/O • Connect through a 50Ω ±1% resistor to Ground.
• Pull up to EP80579 GbE 2.5V Standby (VCCSUS25) supply through a 50Ω
I/O
±1% resistor
• Connect to the MDC signal of the PHY device.
• Provide termination if signal is connected to multiple receivers.
• Resides in GbE Standby Power Well
O
Note:
• Can be left as NC when none of GBE ports is connected to an interfacing
device
• Connect to the MDIO signal of the PHY device.
• Pull-up signal to EP80579 GbE 2.5V Standby (VCCSUS25) using a 1.5 KΩ
± 5% resistor
I/O
Note:
• Must be pulled high through a 10 KΩ resistor to EP80579 GbE 2.5V
Standby (VCCSUS25) when none of GBE ports is connected to an
interfacing device
• Connect to EEPROM Serial Data Output signal (DO)
• Pull-up to corresponding GbE Standby power supply through a 4.7KΩ ±5%
resistor.
I
Note:
• Must be pulled high through a 10 KΩ resistor to EP80579 GbE 2.5V
Standby (VCCSUS25) when none of GBE ports is connected to an
interfacing device
• Connect to EEPROM Serial Data Input signal (DI)
O
• Requires a 20 KΩ pull-up to GbE Standby power if GbE Standby power is generated
on the platform; otherwise pull-down with 4.7 KΩ
• Connect to EEPROM Chip Select input (CS)
• Connect through a 4.7KΩ ±5% resistor to Ground.
O
Note:
• Can be left as NC when none of GBE ports is connected to an interfacing
device
Comments
RMII Mode
• 50 MHz RMII Reference clock.
• Sourced from the same external
clock as GBE_REFCLK
Note:
• In RMII Mode, the GBE_REFCLK,
GBE_REFCLK_RMII, and
PHY_REFCLK are sourced by the
same external 50 MHz clock, hence,
use a no-delay clock buffer to
distribute the clocks to the three
receivers.
• Route clock signals exactly same
length from clock buffer to
receivers.
Order Number: 320068-005US
May 2010