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Electrical Specifications
5.
Specification is for a minimum swing is specified into the test circuit described in
between AGTL+ V
6.
RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
7.
This should be measured after V
8.
Maximum specification applies only while PWRGOOD is asserted.
.
Table 2-21. FSB Source Synchronous AC Specifications
T20: Source Sync. Output Valid Delay
(first data/address only)
T21: T
VBD
Valid Before Data Strobe
T22: T
VAD
Valid After Data Strobe
T23: T
VBA
Valid Before Address Strobe
T24: T
VAA
Valid After Address Strobe
T25: T
SUSS
T25: T
SUSS
T26: T
HSS
T26: T
HSS
T27: Source Synchronous Address
Strobe Setup Time to BCLK[1:0]
T28: Source Synchronous Data Strobe
Setup Time to BCLK[1:0]
T30: Data Strobe 'n' (DSTBN#) Output
Valid Delay
T31: Address Strobe Output Valid Delay
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Not 100% tested. Specified by design characterization.
3.
All source synchronous AC timings are referenced to their associated strobe at nominal
GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END. Source synchronous
data signals are referenced to the falling edge of their associated data strobe. Source synchronous address
signals are referenced to the rising and falling edge of their associated address strobe. All source
synchronous AGTL+ signal timings are referenced at nominal GTLREF_DATA_MID, GTLREF_DATA_END,
GTLREF_ADD_MID, and GTLREF_ADD_END at the processor core (pads).
4.
Unless otherwise noted, these specifications apply to both data and address timings.
5.
Valid delay timings for these signals are specified into the test circuit described in
GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at 0.67 * V
6.
Specification is for a minimum swing into the test circuit described in
AGTL+ V
7.
All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to
each respective strobe.
8.
This specification represents the minimum time the data or address will be valid before its strobe. Refer to
the appropriate platform design guidelines for more information on the definitions and use of these
specifications.
9.
This specification represents the minimum time the data or address will be valid after its strobe. Refer to
the appropriate platform design guidelines for more information on the definitions and use of these
specifications.
10. The rising edge of ADSTB# must come approximately 1/2 BCLK period after the falling edge of ADSTB#.
11. For this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively.
12. The address strobe setup time is measured with respect to T2. Calculation of the setup time is as follows.:
a.
b.
13. This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe.
14. This specification reflects a typical value, not a minimum or maximum.
15. For this timing parameter, n = 0 to 1.
Document Number: 318080-002
to V
. This assumes an edge rate of 2.0 V/ns to 3.0 V/ns.
IL_MAX
IH_MIN
and BCLK[1:0] become stable.
TT
T# Parameter
Source Sync. Data Output
Source Sync. Data Output
Source Sync. Address Output
Source Sync. Address Output
Data Input Setup Time
Address Input Setup Time
Data Input Hold Time
Address Input Hold Time
to V
. This assumes an edge rate of 3.0 V/ns to 5.5 V/ns.
IL_MAX
IH_MIN
If T27 > BCLK period, then the setup time calculated is positive. The value calculated indicates
setup time before T1.
If T27 < BCLK period, then the setup time calculated is negative. The value calculated indicates
setup time after T1. Refer to
Min
Max
0.00
1.10
0.270
0.270
0.660
0.660
0.190
0.300
0.190
0.300
3.5 -
(1.875 * n)
4.15 -
(0.9375 * n)
3.28
4.38
2.81
3.91
Figure
2-17.
Figure 2-11
and defined
1, 2, 3, 4
Unit
Figure
Notes
ns
2-17,
5
2-18
ns
2-18
5,8
ns
2-18
5,9
ns
2-17
5,8
ns
2-17
5,9
ns
2-17 2-18
6
ns
2-17,
6
2-18
ns
2-17,
6
2-18
ns
2-17,
6
2-18
ns
2-17
12, 14, 15
ns
2-18
11,14
ns
2-18
13
ns
2-17
Figure 2-11
and with
.
TT
Figure 2-11
and defined between
41
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