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Low-Power Module Memory Bus Simulation Methodology
Figure 2, shows the Pi-element network model used for the 400-pin module connector.
Figure 2. 400-pin Connector Package Model
C =
0.5 pF
Figure 3 shows the Pi-element network model used for the DIMM connector.
Figure 3. DIMM Connector Package Model
C =
0.9 pF
5.0
Simulation Conditions
The DIMM topology routing for each signal is defined in the 4-Clock 66 MHz 72-Bit ECC
Unbuffered SDRAM DIMM design specification. Figure 4 shows the 2-DIMM system connection
and the possible receiver pin loads for each memory signal. For example, a fully populated x8 with
ECC arrangement for a 2-DIMM system yields the heaviest receiving pin load (2 x 18 = 36 loads)
on the SRAS_A#, SCAS_A#, WE_A#, and MAB# signals, as shown in Table 3. Since the Low-
Power Module is also designed to support a 1-DIMM system, a x16 arrangement DIMM yields the
lightest pin load (four loads) on the same signals.
The heaviest and lightest receiving pin loads for each Low-Power Module memory signal is used
for slow (setup) and fast (hold) corner simulations, respectively.
The DIMMs used for this simulation are x8, x8 with ECC, and x16 DIMM arrangements.
8
R = 0.01 Ohms
R = 0.027 Ohms
L = 3.5 nH
C =
0.5 pF
L = 5 nH
C =
0.9 pF
Application Note
AA6430-01
A6431-01
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