Phy Overview; Phy Interconnects; Quark™ Soc X1000; Rmii Signals - Intel Quark SoC X1000 Design Manual

Table 64. MDIO Data Signals on the Intel
Group
MAC_0 Data
MAC_1 Data
Table 65.

RMII Signals

Group
MAC_0
Data
MAC_0
Data
MAC_1
Data
MAC_1
Data
MAC_0 Ctrl
MAC_0 Ctrl
MAC_1 Ctrl
MAC_1 Ctrl
Table 66.

Clock and Reset Signals

Group
Clock
Clock
Clock
21.1

PHY Overview

The PHY is a single port compact component designed for 10/100Mbps operation. The
PHY provides a standard IEEE 802.3u Ethernet interface for 100BASE-TX, and 10BASE-
T applications.
21.1.1

PHY Interconnects

The main interfaces for either PHY are MDIO and RMII on the host side and Media
Dependent Interface (MDI) on the link side. Transmit traffic is received from the SoC as
RMII packets on the host interconnect and transmitted as Ethernet packets on the MDI
link. Receive traffic arrives as Ethernet packets on the MDI link and transferred to the
SoC through the RMII interconnect.
®
Intel Quark™ SoC X1000
PDG
146
®
Intel Quark™ SoC X1000—LAN Design Considerations and Guidelines
®
Quark™ SoC X1000
PHY Signal Name
MDIO MAC0 MDIO
MDIO MAC1_MDIO
PHY Signal Name
TXD_0
TXD_1
RXD_0
RXD_1
TXD_0
TXD_1
RXD_0
RXD_1
TX_EN
RX_DV
TX_EN
RX_DV
PHY Signal Name
MDC MAC0_MDC
MDC MAC1_MDC
X1 RMII_REF_CLK
SOC Signal Name
SOC Signal Name
MAC0_RXDATA[1:0]
MAC0_TXDATA[1:0]
MAC1_RXDATA[1:0]
MAC1_TXDATA[1:0]
MAC0_TXEN
MAC0_RXDV
MAC1_TXEN
MAC1_RXDV
SOC Signal Name
Description
MDIO data
MDIO data
Description
SoC receive data
SoC transmit data
SoC receive data
SoC transmit data
SoC MAC0 transmit enable
SoC MAC0 Receive data
valid
SoC MAC1 transmit enable
SoC MAC1 Receive data
valid
Description
MAC0 management data
clock
MAC1 management data
clock
RMII PHY reference clock
June 2014
Order Number: 330258-002US