Status Registers Model From Ieee 488.2; Egister M Odel - Ametek Sorensen XG Operation Manual

Status Registers Model from IEEE 488.2

The IEEE 488.2 registers shown in the bottom rectangle of Figure 5-16
follow the IEEE 488.2 model for status registers. The IEEE 488.2
register only has enable registers for masking the summary bits. Figure
5-19 shows the details on the relationship between the mask/enable
registers and the summary bits. Sections describing the bits for both
registers will follow Figure 5-19.
Error/Event Queue Status Flag
QUEStionable SCPI Register
Summary Bit
OPERational SCPI Register
Summary Bit
Standard
Event
Status
Register
(SESR)
SERS
Enable
Register
Figure 5-19 IEEE 488.2 Register Model
M370430-01 Rev B
Status Byte
Register
SESR
Summary
Bit
Status Byte
Enable Register
Remote Operation
MSS
Summary
Bit
5-31
5