Mpc Arbiter Control Register - Motorola MVME2600 Series Reference Manual

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

MPC Arbiter Control Register

2
Address
Bit
0 1 2 3 4 5 6 7 8 9
Name
Operation
Reset
2-28
1 1 1
0 1 2
R R
$00 $00
BREN2 Bus Request 2 Enable. If set, the processor bus request
signal ABR2* is enabled. If cleared, ABR2* is not
enabled, and ABG2* will never be asserted.
BREN1 Bus Request 1 Enable. If set, the processor bus request
signal ABR1* is enabled. If cleared, ABR1* is not
enabled, and ABG1* will never be asserted.
BREN0 Bus Request 0 Enable. If set, the processor bus request
signal ABR0* is enabled. If cleared, ABR0* is not
enabled, and ABG0* will never be asserted.
PKEN Bus Parking Enable. If set, the MPC arbiter will park an
MPC master on the bus when no bus requests are pending.
If cleared, no MPC master will be granted the bus without
first asserting its ABRx*.
PKMD Bus Parking Mode. When bus parking is enabled (PKEN
is set), this bit defines the method used to determine which
MPC master is parked on the bus. If set, the master
specified in the DEFM field is parked on the bus when no
bus requests are pending. If cleared, the last active MPC
master is parked on the bus when no bus requests are
pending. This field has no meaning when PKEN is clear.
$FEFF000C
1 1 1 1 1 1 1 2 2 2
3 4 5 6 7 8 9 0 1 2
2 2 2 2 2 2 2 3 3
3 4 5 6 7 8 9 0 1
MARB