Introduction; Overview - Motorola MVME2600 Series Reference Manual

2Raven PCI Host Bridge & Multi-
Processor Interrupt Controller Chip

Introduction

Overview

This document describes the architecture and usage of the Raven, a
PowerPC to PCI Local Bus Bridge ASIC. The Raven is intended to
provide MPC60x compliant devices access to devices residing on the PCI
Local Bus in a very efficient manner. In the remainder of this chapter, the
MPC60x bus will be referred to as the MPC bus and the PCI Local Bus as
PCI.
No manufacturer currently has plans to support the MPC bus directly.
Therefore, some alternative I/O bus will be necessary in any PowerPC
product. This I/O bus must be robust and efficient enough to handle the
high bandwidth, burst oriented traffic required for Ethernet, SCSI,
graphics, and VMEbus interfaces.
PCI is a high performance 32-bit or 64-bit, burst mode, synchronous bus
capable of transfer rates of 132 MByte/sec in 32-bit mode or 264
MByte/sec in 64-bit mode. While the PCI specification is relatively new,
it has received overwhelming support among PC clone manufacturers.
Many peripheral device manufacturers have designed PCI Local Bus
compliant products. NCR tested a PCI SCSI controller and a PCI Ethernet
controller. Ethernet controllers from AMD and National Semiconductor
are available. Graphics controllers are available from Trident, S3, Oak
Technologies, Weitek, Chips and Technologies, Headland Technologies,
and NCR.
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