Blocks A And/Or B Present, Blocks C And/Or D Present; Dram Arbitration - Motorola MVME2600 Series Reference Manual

Blocks A and/or B Present, Blocks C and/or D present

The Falcon pair performs refresh by doing a burst of four RAS_ cycles
approximately once every 30 s. This increases to once every 15 s when
certain DRAM devices are used. (Controlled by the ram_fref bit in the
status registers.) RAS_ is asserted to blocks A and B during the first cycle,
to blocks C and D during the second cycle, back to blocks A and B during
the third cycle and to blocks C and D during the fourth cycle. Along with
RAS, the Falcon pair also asserts CAS_ with (OE_ then WE_) to one of
the blocks during one of the four cycles. This forms a read-modify-write
which is a scrub cycle to that location.
After the second and fourth cycles, the DRAM row address increments by
one. When it reaches all 1's, it rolls over and starts over at 0. Each time the
row address rolls over, the block that is scrubbed toggles between A/C and
B/D. Every second time the row address rolls over, which of the 4 cycles
that is a scrub changes from 1st to 2nd, from 2nd to 3rd, from 3rd to 4th,
or from 4th to 1st. Every eighth time that the row address rolls over, the
column address increments by one. When the column address reaches all
1's, it rolls over and starts over at 0. Each time the column address rolls
over, the SC1, SC0 bits in the scrub/refresh register increment by one.
Note that an entire refresh of DRAM is achieved every time the row
address rolls over, and that an entire scrub of DRAM is achieved every
time the column address rolls over.
During scrub cycles, if the SWEN bit is cleared, the Falcon pair does not
perform the write portion of the read-modify write cycle. If the SWEN bit
is set, the Falcon pair does perform the write unless it encounters a double-
bit error during the read.
If so enabled, single- and double-bit scrub errors are logged, and the
PowerPC 60x bus master is notified via interrupt.

DRAM Arbitration

The Falcon pair has 3 different entities that can request use of the DRAM
cycle controller:
The PowerPC 60x bus master
Functional Description
3-21
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