Motorola MVME2600 Series Reference Manual page 123

Mvme2600/2700 series single board computer
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Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
2
2-56
when the priority of the interrupt is greater than the priority contained in
the task register for that processor, and when the priority of the interrupt is
greater than any interrupt which is in-service for that processor. An
interrupt is considered to be in service from the time its vector is returned
during an interrupt acknowledge cycle until an EOI is received for that
interrupt. The EOI cycle indicates the end of processing for the highest
priority in- service interrupt.
In the distributed delivery mode, the interrupt is pointed to one or more
processors but it will be delivered to only one processor. Therefore, for
externally sourced or I/O interrupts, multicast delivery is not
supported.The interrupt is delivered to a processor when the priority of the
interrupt is greater than the priority contained in the task register for that
processor, and when the priority of the interrupt is greater than any
interrupt which is in-service for that processor, and when the priority of
that interrupt is the highest of all interrupts pending for that processor, and
when that interrupt is not in-service for the other processor. If both
destination bits are set for each processor, the interrupt will be delivered to
the processor that has a lower task register priority.
Note
Because a deadlock condition can occur when the task
register priorities for each processor are the same and both
processors are targeted for interrupt delivery, the interrupt
will be delivered to processor 0.

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