Pci Configuration Space; Pci Write Posting - Motorola MVME2600 Series Reference Manual

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
2
:

PCI Configuration Space

PCI Write Posting

2-12
Decoder
PCI Slave 0
PCI Slave 1
PCI Slave 2
PCI Slave 3
The Raven does not have an IDSEL pin. An internal connection is made
within the Raven that logically associates the assertion of IDSEL with the
assertion of either AD30 or AD31. The exact association depends on the
state of the EXT02 pin when the RST* pin is released. If EXT02 is
sampled low, the Raven will associate AD30 with IDSEL. If EXT02 is
sampled high, the Raven will associate AD31 with IDSEL.
If write posting is enabled, the Raven stores the target address, attributes,
and up to 128 bytes of data from one PCI write transaction and
immediately acknowledges the transaction on the PCI bus. This allows the
slower PCI to continue to transfer data at its maximum bandwidth, and the
faster MPC bus to accept data in high performance cache-line burst
transfers.
Only one PCI transaction may be write posted at any given time. If the
Raven is busy processing a previous write posted transaction when a new
PCI transaction begins, the next PCI transaction will be delayed (TRDY*
will not be asserted) until the previous transaction has completed. If during
a transaction the write post buffer gets full, subsequent PCI data transfers
will be delayed (TRDY* will not be asserted) until the Raven has removed
some data from the FIFO. Under normal conditions, the Raven should be
able to empty the FIFO faster than the PCI bus can fill it.
PCI Configuration cycles intended for internal Raven registers will also be
delayed if Raven is busy so that control bits which may affect write posting
do not change until all write posted transactions have completed.
Priority
highest
lowest