Motorola MVME2600 Series Reference Manual page 191

Falcon ECC Memory Controller Chip Set
3
3-40
1. During reads, data is presented to the PowerPC 60x data bus
unaltered from the DRAM array.
2. During single-beat writes, data is written without correcting single-
bit errors that may occur on the read portion of the read-modify-
write. Check-bits are generated for the data being written.
3. During single-beat writes, the write portion of the read-modify-
write happens regardless of whether there is a multiple-bit error
during the read portion. No correction of data is attempted. Check-
bits are generated for the data being written.
4. During refresh/scrub cycles, if swen is set, a read-write to DRAM
happens with no attempt to correct data bits. Check-bits are
generated for the data being written.
derc should be cleared during normal system operation.
scien When scien is set, the rolling over of the SBE COUNT
register causes the INT_ signal pin to pulse true.
tien When tien is set, the setting of the tpass or the tfail bit
causes the INT_ signal pin to pulse true.
sien When sien is set, the logging of a single-bit error causes
the INT_ signal pin to pulse true.
mien When mien is set, the logging of a non-correctable error
causes the INT_ signal pin to pulse true.
mcken When mcken is set, the detection of a multiple-bit error
during a PowerPC read or write causes the Falcon to assert
its machine check interrupt request pin (MCP_). When it
is cleared, the Falcon does not ever assert its MCP_ pin.
The Falcon never asserts its MCP_ pin in response to a
multiple-bit error detected during a scrub cycle.