Motorola RAM200-04X Manuals

Manuals and User Guides for Motorola RAM200-04X. We have 1 Motorola RAM200-04X manual available for free PDF download: Reference Manual

Motorola RAM200-04X Reference Manual

Motorola RAM200-04X Reference Manual (283 pages)

MVME2600/2700 Series Single Board Computer

Brand: Motorola | Category: Motherboard | Size: 0.86 MB

Table of Contents

Do Not Operate in an Explosive Atmosphere
5
Do Not Substitute Parts or Modify Equipment
5
Ground the Instrument
5
Keep Away from Live Circuits
5
Use Caution When Exposing or Handling the Crt
5
Table of Contents
6
Introduction
18
Revision Note
18
Manual Terminology
19
Overview
20
Feature Summary
21
Table 1-1. MVME2600 Series Features Summary
21
System Block Diagram
22
CHAPTER 1 Board Description and Memory Maps

23
CHAPTER 2 Raven PCI Host Bridge & Multi-Processor Interrupt Controller

68
- Introduction
  68
  - Overview
    68
  - Requirements
    69
  - Features
    69
- Block Diagram
  71
- Figure 2-1. Raven Block Diagram
  71
- Functional Description
  72
  - MPC Bus Interface
    72
    
    MPC Arbiter
    72
    
    MPC Map Decoders
    74
    
    Table 2-1. CHRP Compliant Memory Map
    74
    
    MPC Write Posting
    75
    
    MPC Master
    76
    
    MPC Bus Timer
    77
    
    Table 2-2. MPC Transfer Types
    77
  - PCI Interface
    78
    
    PCI Map Decoders
    78
    
    PCI Configuration Space
    79
    
    PCI Write Posting
    79
    
    PCI Master
    80
  - Generating PCI Memory and I/O Cycles
    80
  - Table 2-3. PCI Command Codes
    80
  - Figure 2-2. PCI Spread I/O Cycle Mapping
    81
  - Generating PCI Configuration Cycles
    82
  - Generating PCI Special Cycles
    82
  - Generating PCI Interrupt Acknowledge Cycles
    83
  - Endian Conversion
    83
    
    When MPC Devices Are Big-Endian
    83
    
    When MPC Devices Are Little Endian
    84
    
    Figure 2-3. Big to Little Endian Data Swap
    84
    
    Cycles Originating from PCI
    85
  - Error Handling
    85
  - Table 2-4. Address Modification for Little Endian Transfers
    85
  - PCI/MPC Contention Handling
    87
- Registers
  89
  - MPC Registers
    89
    
    Table 2-5. Raven MPC Register Map
    89
    
    Revision ID Register
    91
    
    Vendor ID/Device ID Registers
    91
    
    General Control-Status/Feature Registers
    92
    
    MPC Arbiter Control Register
    95
    
    Prescaler Adjust Register
    96
    
    MPC Error Enable Register
    97
    
    MPC Error Status Register
    99
    
    MPC Error Address Register
    101
    
    MPC Error Attribute Register - MERAT
    101
    
    PCI Interrupt Acknowledge Register
    103
    
    MPC Slave Address (0,1 and 2) Registers
    104
    
    MPC Slave Address (3) Register
    105
    
    MPC Slave Offset/Attribute (0,1 and 2) Registers
    106
    
    MPC Slave Offset/Attribute (3) Registers
    107
    
    General Purpose Registers
    108
  - PCI Registers
    108
    
    Table 2-6. Raven PCI Configuration Register Map
    109
    
    Table 2-7. Raven PCI I/O Register Map
    109
    
    PCI Command/ Status Registers
    110
    
    Vendor ID/ Device ID Registers
    110
    
    Revision ID/ Class Code Registers
    112
    
    I/O Base Register
    113
    
    Memory Base Register
    113
    
    PCI Slave Address (0,1,2 and 3) Registers
    114
    
    PCI Slave Attribute/ Offset (0,1,2 and 3) Registers
    115
    
    Config_Address
    116
    
    PCI I/O CONFIG_ADDRESS Register
    117
    
    PCI I/O CONFIG_DATA Register
    118
- Raven Interrupt Controller Implementation
  119
  - Architecture
    119
  - Introduction
    119
  - The Raven Interrupt Controller (Ravenmpic) Features
    119
  - Csr's Readability
    120
  - Interrupt Source Priority
    120
  - Nesting of Interrupt Events
    120
  - Processor's Current Task Priority
    120
  - Compatibility
    121
  - Interprocessor Interrupts (IPI)
    121
  - Spurious Vector Generation
    121
  - Interrupt Delivery Modes
    122
  - Raven-Detected Errors
    122
  - Timers
    122
  - Block Diagram Description
    124
    
    Program Visible Registers
    125
    
    Interrupt Pending Register (IPR)
    125
    
    Interrupt Selector (IS)
    125
    
    Interrupt Request Register (IRR)
    126
    
    In-Service Register (ISR)
    126
    
    Interrupt Router
    126
    
    Table 2-8. Ravenmpic Register Map
    128
  - Figure 2-4. Ravenmpic Block Diagram
    124
  - MPIC Registers
    128
    
    Ravenmpic Registers
    128
    
    Feature Reporting Register
    132
    
    Global Configuration Register
    133
    
    Vendor Identification Register
    134
    
    Processor Init Register
    134
    
    IPI Vector/Priority Registers
    135
    
    Spurious Vector Register
    136
    
    Timer Frequency Register
    136
    
    Timer Current Count Registers
    137
    
    Timer Basecount Registers
    137
    
    Timer Vector/Priority Registers
    138
    
    Timer Destination Registers
    139
    
    External Source Vector/Priority Registers
    139
    
    External Source Destination Registers
    141
    
    Raven-Detected Errors Vector/Priority Register
    141
    
    Raven-Detected Errors Destination Register
    142
    
    Interprocessor Interrupt Dispatch Registers
    143
    
    Interrupt Task Priority Registers
    143
    
    Interrupt Acknowledge Registers
    145
    
    End-Of-Interrupt Registers
    145
  - Programming Notes
    146
    
    External Interrupt Service
    146
    
    Reset State
    147
  - Operation
    148
    
    Interprocessor Interrupts
    148
    
    Dynamically Changing I/O Interrupt Configuration
    148
    
    EOI Register
    148
    
    Interrupt Acknowledge Register
    149
    
    Mode
    149
    
    Current Task Priority Level
    149
  - Architectural Notes
    149
CHAPTER 3 Falcon ECC Memory Controller Chip Set

152
- Bit Ordering Convention
  152
  - Introduction
    152
  - Overview
    152
  - Features
    152
- Block Diagrams
  153
- Functional Description
  157
  - Four-Beat Reads/Writes
    157
  - Single-Beat Reads/Writes
    158
  - DRAM Speeds
    158
  - Table 3-1. Powerpc 60X Bus to DRAM Access Timing When Configured for
    159
  - Table 3-2. Powerpc 60X Bus to DRAM Access Timing When Configured for 60Ns
    160
  - Table 3-3. Powerpc 60X Bus to DRAM Access Timing When Configured for 50Ns Hyper Devices
    161
  - Table 3-4. Powerpc 60X Bus to Rom/Flash Access Timing When
    162
  - Table 3-5. Powerpc 60X Bus to Rom/Flash Access Timing When Configured for 8-Bit Devices
    162
  - Rom/Flash Speeds
    162
  - Powerpc 60X Bus Interface
    163
    
    Responding to Address Transfers
    163
    
    Completing Data Transfers
    163
    
    Cache Coherency
    163
    
    Cache Coherency Restrictions
    164
    
    L2 Cache Support
    164
    
    Cycle Types
    164
    
    Error Reporting
    164
    
    Table 3-6. Error Reporting
    165
    
    Error Logging
    166
  - DRAM Tester
    166
  - Rom/Flash Interface
    167
  - Table 3-7. Powerpc 60X to Rom/Flash Address Mapping with Two
    168
  - Table 3-8. Powerpc 60X Address to Rom/Flash Address Mapping with Two 32-Bit or One 64-Bit Device(S)
    170
  - Refresh/Scrub
    171
    
    Blocks a And/Or B Present, Blocks C and D Not Present
    171
    
    Blocks a And/Or B Present, Blocks C And/Or D Present
    172
  - DRAM Arbitration
    172
  - Chip Defaults
    173
    
    External Register Set
    173
  - CSR Accesses
    174
  - Figure 3-4. Data Path for Reads from the Falcon Internal Csrs
    175
  - CSR Architecture
    175
  - Programming Model
    175
  - Figure 3-5. Data Path for Writes to the Falcon Internal Csrs
    176
  - Figure 3-6. Memory Map for Byte Reads to the CSR
    177
  - Figure 3-7. Memory Map for Byte Writes to the Internal Register Set and
    178
  - Figure 3-8. Memory Map for 4-Byte Reads to the CSR
    179
  - Figure 3-9. Memory Map for 4-Byte Writes to the Internal Register Set and Test SRAM
    179
  - Register Summary
    180
  - Table 3-9. Register Summary
    181
  - Detailed Register Bit Descriptions
    183
    
    Vendor/Device Register
    184
    
    Revision ID/ General Control Register
    185
    
    Table 3-10. Ram Spd1,Ram Spd0 and DRAM Type
    186
    
    Table 3-11. Block_A/B/C/D Configurations
    187
    
    DRAM Attributes Register
    187
    
    DRAM Base Register
    188
    
    CLK Frequency Register
    189
    
    ECC Control Register
    189
    
    Error Logger Register
    192
    
    Error_Address Register
    194
    
    Scrub/Refresh Register
    194
    
    Table 3-12. Rtest Encodings
    195
    
    Refresh/Scrub Address Register
    195
    
    ROM a Base/Size Register
    196
    
    Table 3-13. ROM Block a Size Encoding
    197
    
    Table 3-15. Read/Write to Rom/Flash
    198
    
    ROM B Base/Size Register
    199
    
    Table 3-16. ROM Block B Size Encoding
    201
    
    DRAM Tester Control Registers
    202
    
    Bit Counter
    202
    
    Test SRAM
    203
    
    Power-Up Reset Status Register 1
    204
    
    Power-Up Reset Status Register 2
    204
    
    External Register Set
    205
- Software Considerations
  206
- ECC Codes
  210
- Table 3-20. Single-Bit Errors Ordered by Syndrome Code
  211
- Data Paths
  212
- Figure 3-10. Powerpc Data to DRAM Data Correspondence
  213
- Table 3-21. Powerpc Data to DRAM Data Mapping
  214
CHAPTER 4 Universe (Vmebus to PCI) Chip

216
- General Information
  216
  - Introduction
    216
  - Product Overview - Features
    216
  - Architectural Overview
    217
    
    Functional Description
    217
    
    Dma Controller
    218
    
    Figure 4-1. Architectural Diagram for the Universe
    218
    
    Interrupter and Interrupt Handler
    218
    
    Pci Bus Interface
    218
    
    Vmebus Interface
    219
    
    PCI Bus Interface
    220
    
    Interrupter and Interrupt Handler
    221
    
    DMA Controller
    222
- Registers - Universe Control and Status Registers (UCSR)
  222
  - Figure 4-2. UCSR Access Mechanisms
    223
  - Universe Register Map
    223
  - Table 4-1. Universe Register Map
    224
- PCI Reset Problems Associated with the Initial Version of the Universe Chip
  229
  - Problem Description
    229
  - Examples
    231
    
    Example 1: MVME2600 Series Board Exhibits Problem
    231
    
    Example 2: MVME3600 Series Board Acts Differently
    233
    
    Example 3: Universe Chip Is Checked at Tundra
    235
    
    Table 5-1. PCI Arbitration Assignments
    236
CHAPTER 5 Programming Details

236
- Introduction
  236
- Figure 5-1. MVME2600/2700 Series Interrupt Architecture
  237
- Interrupt Handling
  237
  - Ravenmpic
    238
  - Table 5-2. Ravenmpic Interrupt Assignments
    238
  - Interrupts
    239
  - Figure 5-2. PIB Interrupt Handler Block Diagram
    240
  - Table 5-3. PIB PCI/ISA Interrupt Assignments
    241
  - ISA DMA Channels
    242
- Exceptions
  243
  - Sources of Reset
    243
  - Table 5-4. Reset Sources and Devices Affected
    244
  - Soft Reset
    244
  - Universe Chip Problems after a PCI Reset
    244
  - Table 5-5. Error Notification and Handling
    245
- Endian Issues
  246
  - Figure 5-3. Big-Endian Mode
    247
  - Figure 5-4. Little-Endian Mode
    248
  - PCI Domain
    249
    
    Pci-Scsi
    249
    
    PCI-Ethernet
    250
    
    PCI-Graphics
    250
  - Processor/Memory Domain
    249
  - Raven's Involvement
    249
  - Universe's Involvement
    250
  - Vmebus Domain
    250
  - Table 5-6. ROM/FLASH Bank Default
    251
- Rom/Flash Initialization
  251
- Overview
  252
APPENDIX A Related Documentation

253
- MCG Customer Services
  253
- Abbreviations, Acronyms, and Terms to Know
  264

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