Cpu Control Register - Motorola MVME2600 Series Reference Manual

CPU Control Register

The CPU Control Register is accessed via the RD[32:39] data lines of the
upper Falcon device. This 8-bit register is defined as follows:
REG
BIT 0
FIELD
OPER R
RESET X
LEMODE Little Endian Mode. This bit must be set in conjunction
P0/1_TBENProcessor 0/1 Time Base Enable. When this bit is cleared,
CPU Control Register - $FEF88300
1 2 3
R R/W R/W
0 1 1
with the LEND bit in the Raven for little-endian mode.
the TBEN pin of Processor 0/1 will be driven low.
Programming Model
4 5 6
R R R
X X X
1
7
R
X
1-33