Raven Interrupt Controller Implementation; Introduction; The Raven Interrupt Controller (Ravenmpic) Features; Architecture - Motorola MVME2600 Series Reference Manual

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
2Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
2

Raven Interrupt Controller Implementation

Introduction

The Raven Interrupt Controller (RavenMPIC) Features

Architecture

2-52
MPIC programming model
Support for two processors
Support for 16 external interrupts
Support for 15 programmable Interrupt & Processor Task priority
levels
Support for the connection of an external 8259 for ISA/AT
compatibility
Distributed interrupt delivery for external I/O interrupts
Direct/Multicast interrupt delivery for Interprocessor and timer
interrupts
Four Interprocessor Interrupt sources
Four timers
Processor initialization control
The Raven PCI Slave implements two address decoders for placing the
RavenMPIC registers in PCI IO or PCI Memory space. Access to these
registers require MPC and PCI bus mastership. These accesses include
interrupt and timer initialization and interrupt vector reads.
The RavenMPIC receives interrupt inputs from 16 external sources, four
interprocessor sources, four timer sources, and one Raven internal error
detection source. The externally sourced interrupts 1 through 15 have two