Clk Frequency Register; Ecc Control Register - Motorola MVME2600 Series Reference Manual

Falcon ECC Memory Controller Chip Set

CLK Frequency Register

ADDRESS
3 BIT
CLK FREQUENCY
NAME
OPERATIO
READ/WRITE
N
RESET

ECC Control Register

ADDRESS
BIT
NAME
OPERATIO
N
RESET
3-38
READ ZERO
42 P X
CLK FREQUENCY
hexadecimal value of the operating CLOCK frequency in
MHz (i.e. $42 for 66MHz). When these bits are
programmed this way, the chip's prescale counter
produces a 1MHz output. The output of the chip prescale
counter is used by the refresher/scrubber and the 32-bit
counter. After power-up, this register is initialized to $42
(for 66MHz).
por por is set by the occurrence of power up reset. It is cleared
by writing a one to it. Writing a 0 to it has no effect.
refdis When set, refdis causes the refresher and all of its
associated counters and state machines to be cleared and
maintained that way until refdis is removed (cleared). If a
refresh cycle is in process when refdis is updated by a
write to this register, the update does not take effect until
$FEF80020
READ ZERO
X
These bits should be programmed with the
$FEF80028
READ ZERO
X