Vendor Identification Register; Processor Init Register - Motorola MVME2600 Series Reference Manual
Mvme2600/2700 series single board computer
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Also See for MVME2600 Series:
- Installation and use manual (198 pages) ,
- Installation and use manual (20 pages) ,
- Programmer's reference manual (20 pages)
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0Raven Interrupt Controller Implementation
Vendor Identification Register
Offset
Bit
3
3
2
2
2
1
0
9
8
7
Name
Operation
R
Reset
$00
There are two fields in the Vendor Identification Register which are not
defined for the RavenMPIC implementation but are defined in the MPIC
specification. They are the vendor identification and device ID fields.
STP
Processor Init Register
Offset
Bit
3
3
2
2
2
1
0
9
8
7
Name
Operation
R
Reset
$00
P1
P0
2Raven PCI Host Bridge & Multi-Processor Interrupt
Controller Chip
$01080
2
2
2
2
2
2
2
1
1
1
6
5
4
3
2
1
0
9
8
7
VENDOR IDENTIFICATION
STP
R
$02
STEPPING.The stepping or silicon revision number is
initially 0.
$01090
2
2
2
2
2
2
2
1
1
1
6
5
4
3
2
1
0
9
8
7
PROCESSOR INIT
R
$00
PROCESSOR 1. Writing a 1 to P1 will assert the Soft
Reset input of processor 1. Writing a 0 to it will negate the
SRESET signal.
PROCESSOR 0. Writing a 1 to P0 will assert the Soft
Reset input of processor 0. Writing a 0 to it will negate the
SRESET signal.
Raven Interrupt Controller Implementation
1
1
1
1
1
1
1
6
5
4
3
2
1
0 9 8 7 6 5 4 3 2 1 0
R
$00
1
1
1
1
1
1
1
6
5
4
3
2
1
0 9 8 7 6 5 4 3 2 1 0
R
$00
2
R
$00
R
$00
2-67
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