Table 3-3. Powerpc 60X Bus To Dram Access Timing When Configured For 50Ns Hyper Devices - Motorola MVME2600 Series Reference Manual

Falcon ECC Memory Controller Chip Set
Table 3-3. PowerPC 60x Bus to DRAM Access Timing When Configured for
3
ACCESS TYPE
4-Beat Read after Idle (Quad-word
aligned)
4-Beat Read after Idle (Quad-word
misaligned)
4-Beat Read after 4-Beat Read
(Quad-word aligned)
4-Beat Read after 4-Beat Read
(misaligned)
4-Beat Write after Idle
4-Beat Write after 4-Beat Write
(Quad-word aligned)
1-Beat Read after Idle
1-Beat Read after 1-Beat Read
1-Beat Write after Idle
1-Beat Write after 1-Beat Write
3-10
50ns Hyper Devices
CLOCK PERIODS REQUIRED FOR:
Beat
5/2
4/2
4/3
7/5
9/7
Notes:
1. These numbers assume that the PowerPC 60x bus master is doing
address pipelining with TS_ occurring at the minimum time after
AACK_ is asserted. Also the two numbers shown in 1st beat column
are for page hit/page miss.
2. In some cases, the numbers shown are averages and specific
instances may be longer or shorter.
1st 2nd 3rd
Beat Beat
8 1
8 2
1
1
1
2
4 1
1
1
-
8
1
-
-
4
-
1
Total
4th
Clocks
Beat
1 1 11
1 1 12
1 1 8/5
1 1 8/6
1 1 7
1 1 7/6
- - 8
7/5
- -
- - 4
- - 9/7