Motorola MVME2600 Series Reference Manual page 111

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
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MEMSP Memory Space Enable. If set, the Raven will respond to
PCI memory space accesses when appropriate. If cleared,
the Raven will not respond to PCI memory space
accesses.
MSTR Bus Master Enable. If set, the Raven may act as a master
on PCI. If cleared, the Raven may not act as a PCI master.
PERR Parity Error Response. If set, the Raven will check
parity on all PCI transfers. If cleared, the Raven will
ignore any parity errors that it detects and continue normal
operation.
SERR System Error Enable. This bit enables the SERR* output
pin. If clear, the Raven will never drive SERR*. If set, the
Raven will drive SERR* active when a system error is
detected.
FAST Fast Back-to-Back Capable. This bit indicates that the
Raven is capable of accepting fast back-to-back
transactions with different targets.
DPAR Data Parity Detected. This bit is set when three
conditions are met: 1) the Raven asserted PERR* itself or
observed PERR* asserted; 2) the Raven was the PCI
master for the transfer in which the error occurred; 3) the
PERR bit in the PCI Command Register is set. This bit is
cleared by writing it to 1; writing a 0 has no effect.
SELTIM DEVSEL Timing. This field indicates that the Raven will
always assert DEVSEL* as a 'medium' responder.
SIGTA Signalled Target Abort. This bit is set by the PCI slave
whenever it terminates a transaction with a target-abort. It
is cleared by writing it to 1; writing a 0 has no effect.
RCVTA Received Target Abort. This bit is set by the PCI master
whenever its transaction is terminated by a target-abort. It
is cleared by writing it to 1; writing a 0 has no effect.