Interrupt Acknowledge Register; Mode; Current Task Priority Level; Architectural Notes - Motorola MVME2600 Series Reference Manual

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
2

Interrupt Acknowledge Register

8259 Mode

Current Task Priority Level

Architectural Notes

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highest priority source. Once an interrupt is acknowledged, only sources
of higher priority will be allowed to interrupt the processor until the EOI
command is received. This register should always be written with a value
of zero which is the nonspecific EOI command.
Upon receipt of an interrupt signal, the processor may read this register to
retrieve the vector of the interrupt source which caused the interrupt.
The 8259 mode bits control the use of an external 8259 pair for PC-AT
compatibility. Following a reset, this mode is set for pass-through, which
essentially disables the advanced controller and passes an 8259 input on
external interrupt source 0 directly through to processor zero. During
interrupt controller initialization this channel should be programmed for
mixed mode in order to take advantage of the interrupt delivery modes.
Each processor has a separate Current Task Priority Level register. The
system software uses this register to indicate the relative priority of the task
running on the corresponding processor. The interrupt controller will not
deliver an interrupt to a processor unless it has a priority level which is
greater than the current task priority level of that processor. This value is
also used in determining the destination for interrupts which are delivered
using the distributed deliver mode.
The hardware and software overhead required to update the task priority
register synchronously with instruction execution may far outweigh the
anticipated benefits of the task priority register. To minimize this
overhead, the interrupt controller architecture should allow the task
priority register to be updated asynchronously with respect to instruction
execution. Lower priority interrupts may continue to occur for an
indeterminate number of cycles after the processor has updated the task
priority register. If this is not acceptable, the interrupt controller