Interprocessor Interrupt Dispatch Registers; Interrupt Task Priority Registers - Motorola MVME2600 Series Reference Manual
Mvme2600/2700 series single board computer
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Also See for MVME2600 Series:
- Installation and use manual (198 pages) ,
- Installation and use manual (20 pages) ,
- Programmer's reference manual (20 pages)
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Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
Interprocessor Interrupt Dispatch Registers
2
Offset
Bit
3
1
Name
Operation
Reset
Interrupt Task Priority Registers
Offset
Bit
3
1
Name
Operation
Reset
2-76
Processor 0 $20040, $20050, $20060, $20070
Processor 1 $21040, $21050,$21060, $21070
3
2
2
2
2
2
2
2
2
2
0
9
8
7
6
5
4
3
2
1
R
$00
There are four Interprocessor Interrupt Dispatch Registers. Writing to an
IPI Dispatch Register with the P0 and/or P1 bit set causes an interprocessor
interrupt request to be sent to one or more processors. Note that each IPI
Dispatch Register has two addresses. These registers are considered to be
per processor registers and there is one address per processor. Reading
these registers returns zeros.
P1
PROCESSOR 1. The interrupt is directed to processor 1.
P0
PROCESSOR 0. The interrupt is directed to processor 0.
3
2
2
2
2
2
2
2
2
2
0
9
8
7
6
5
4
3
2
1
INTERRUPT TASK PRIORITY
R
$00
2
1
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
2
1
IPI DISPATCH
R
R
$00
$00
Processor 0 $20080
Processor 1 $21080
2
1
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
2
1
R
R
$00
$00
1
0 9 8 7 6 5 4 3 2 1 0
R
$00
1
0 9 8 7 6 5 4 3 2 1 0
TP
R
R/W
$0
$F
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