General Control-Status/Feature Registers - Motorola MVME2600 Series Reference Manual

General Control-Status/Feature Registers

Address
Bit
0 1 2 3 4 5 6 7 8 9
Name
Operation
Reset
LEND
FLBRD
BHOG
$FEFF0008
1 1 1 1 1 1
0 1 2 3 4 5
GCSR
Endian Select. If set, the MPC bus is operating in little
endian mode. The MPC address will be modified as
described in the section When MPC Devices are Little
Endian. When LEND is clear, the MPC bus is operating
in big endian mode, and all data to/from PCI is swapped
as described in the section When MPC Devices are Big-
Endian.
Flush Before Read. If set, the Raven will guarantee that
all PCI initiated posted write transactions will be
completed before any MPC initiated read transactions will
be allowed to complete. When FLBRD is clear, there will
be no correlation between these transaction types and
their order of completion. Please refer to the section on
PCI/MPC Contention Handling for more information.
Bus Hog. If set, the Raven MPC master will operate in the
Bus Hog mode. Bus Hog mode means the MPC master
will continually request the MPC bus for the entire
duration of each PCI transfer. If Bus Hog is not enabled,
the MPC master will request the bus in a normal manner.
Please refer to the section on MPC Master for more
information.
1 1 1 1 2 2 2 2 2 2
6 7 8 9 0 1 2 3 4 5
FEAT
Registers
2
2 2 2 2 3 3
6 7 8 9 0 1
2-25