Mpc Master - Motorola MVME2600 Series Reference Manual

All write posted transfers will be completed before a non-write posted read
or write is begun to assure that all transfers are completed in the order
issued. All write posted transfers will also be completed before any access
to the Raven's registers is begun.

MPC Master

Wherever possible, the MPC master will attempt to consolidate data
movement into a pair of burst transfers called couplets. If there is not
enough data movement to perform a couplet, the MPC master will attempt
singular burst transfers. The MPC master will perform single beat transfers
as required during all non-cache aligned writes and some non-cache
aligned reads. A 64-bit by 16 entry FIFO is used to hold data between the
PCI slave and the MPC master to ensure that optimum data throughput is
maintained. While the PCI slave is filling the FIFO with one cache line
worth of data, the MPC master can be moving another cache line worth
onto the MPC bus. This will allow the PCI slave to receive long block
transfers without stalling.
When programmed in "read ahead" mode (the RAEN bit in the PSATTx
register is set) and the PCI slave receives a Memory Read Line or Memory
Read Multiple command, the MPC master will fetch data in bursts and
store it in the FIFO. The contents of the FIFO will then be used to attempt
to satisfy the data requirements for the remainder of the PCI block
transaction. If the data requested is not in the FIFO, the MPC master will
read another cache line. The contents of the FIFO are "invalidated" at the
end of each PCI block transaction.
Notes 1. Read ahead mode should not be used when data coherency
The MPC bus transfer types generated by the MPC master depend on the
PCI command code and the INV bit in the PSATTx registers.
may be a problem as there is no way to snoop all MPC bus
transactions and invalidate the contents of the FIFO.
2. Accesses near the top of local memory with read-ahead
mode enabled could cause the MPC master to perform reads
beyond the top of local memory which could result in an
MPC bus timeout error.
Functional Description
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