Vmebus Interface - Motorola MVME2600 Series Reference Manual

Universe (VMEbus to PCI) Chip

VMEbus Interface

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Universe as VMEbus Slave
The Universe VME Slave Channel accepts all of the addressing and data
transfer modes documented in the VME64 specification (except A64 and
those intended to support 3U applications, i.e. A40 and MD32). Incoming
write transactions from the VMEbus may be treated as either coupled or
posted, depending upon the programming of the VMEbus slave image.
(Refer to VME Slave Images in the Universe User Manual.) With posted
write transactions, data is written to a Posted Write Receive FIFO
(RXFIFO), and the VMEbus master receives data acknowledgment from
the Universe. Write data is transferred to the PCI resource from the
RXFIFO without the involvement of the initiating VMEbus master (Refer
to Posted Writes in the Universe User Manual for a full explanation of this
operation.). With a coupled cycle, the VMEbus master only receives data
acknowledgment when the transaction is complete on the PCI bus. This
means that the VMEbus is unavailable to other masters while the PCI bus
transaction is executed.
Read transactions may be prefetched or coupled. If enabled by the user, a
prefetched read is initiated when a VMEbus master requests a block read
transaction (BLT or MBLT) and this mode is enabled. When the Universe
receives the block read request, it begins to fill its Read Data FIFO
(RDFIFO) using burst transactions from the PCI resource. The initiating
VMEbus master then acquires its block read data from the RDFIFO rather
than from the PCI resources directly.
Universe as VMEbus Master
The Universe becomes VMEbus master when the VME Master Interface
is internally requested by the PCI Bus Slave Channel, the DMA Channel,
or the Interrupt Channel. The Interrupt Channel always has priority over
the other two channels. Several mechanisms are available to configure the
relative priority that the PCI Bus Slave Channel and DMA Channel have
over ownership of the VMEbus Master Interface.
The Universe's VME Master Interface generates all of the addressing and
data transfer modes documented in the VME64 specification (except A64
and those intended to support 3U applications, i.e. A40 and MD32). The