System External Cache Control Register (Sxccr) - Motorola MTX Series Programmer's Reference Manual

Board Description and Memory Maps
1

System External Cache Control Register (SXCCR)

Register
Bit 0
Field
Operation
Reset 1
1-20
Flash Size FLSHP0_
1MB 0
2MB 0
4MB 0
8MB 0
16MB 1
32MB 1
64MB 1
No Flash 1
The System Cache Control Register is accessed via the RD[32:39] data
lines of the upper Falcon device. This 8-bit register is defined as follows:
System External Cache Control Register - $FEF88000
1 2
1 1
SXC_DIS_ System External Cache Enable. When this bit is cleared, it
disables this cache from responding to any bus cycles.
SXC_FLSH_ System External Cache Flush. When this bit is pulsed true
for at least 8 clock periods, it causes the system external cache to write
back dirty cache lines out to system memory and clears all the tag valid
bits.
FLSHP1_ FLSHP2_
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
3 4 5
R/W
1 X X
Computer Group Literature Center Web Site
6 7
X X