Motorola MVME2600 Series Reference Manual page 102

MIDx
TBST
TSIZx
TTx
If the SMA or RTA bit are set the register is defined by the following
figure:
Address
Bit
0 1 2 3 4 5 6 7 8 9
Name
Operation R
Reset $00
WP
MIDx
COMMx PCI Command. This field contains the PCI command of
MPC Master ID. This field contains the ID of the MPC
master which originated the transfer in which the error
occurred. The encoding scheme is identical to that used in
the GCSR register.
Transfer Burst. This bit is set when the transfer in which
the error occurred was a burst transfer.
Transfer Size. This field contains the transfer size of the
MPC transfer in which the error occurred.
Transfer Type. This field contains the transfer type of the
MPC transfer in which the error occurred.
$FEFF002C
1 1 1 1 1 1 1 1
0 1 2 3 4 5 6 7
R
$00
Write Post Completion. This bit is set when the PCI
master detects an error while completing a write post
transfer.
MPC Master ID. This field contains the ID of the MPC
master which originated the transfer in which the error
occurred. The encoding scheme is identical to that used in
the GCSR register
the PCI transfer in which the error occurred.
1 1 2 2 2 2 2 2 2 2
8 9 0 1 2 3 4 5 6 7
MERAT
Registers
2
2 2 3 3
8 9 0 1
2-35