Ppc Arbiter/Pci Arbiter Control Registers - Motorola MVME5100 Programmer's Reference Manual

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

PPC Arbiter/PCI Arbiter Control Registers

2
Address
Bit
0 1 2 3 4 5 6 7 8 9
Name
Operation
Reset
2-72
The PPC Arbiter Register (XARB) provides control and status for the PPC
Arbiter. Refer to the section titled
bits within the XARB register are defined as follows:
1
0
XARB
RW
0
FBRx Flatten Burst Read. This field is used by the PPC Arbiter
to control how bus pipelining will be affected after all
burst read cycles. The encoding of this field is shown in
the table below.
FSRx Flatten Single Read. This field is used by the PPC
Arbiter to control how bus pipelining will be affected after
all single beat read cycles. The encoding of this field is
shown in the table below.
FBWx Flastten Burst Write. This field is used by the PPC
Arbiter to control how bus pipelining will be affected after
all burst write cycles. The encoding of this field is shown
in the table below.
FSWx Flatten Single Write. This field is used by the PPC
Arbiter to control how bus pipelining will be affected after
all single beat write cycles. The encoding of this field is
shown in the table below.
FBR/FSR/FBW/FSW
00
01
10
11
PPC Arbiter
$FEFF000C
1 1 1 1 1 1 1 1 1
1 2 3 4 5 6 7 8 9
Effects on Bus Pipelining
None
None
Flatten always
Flatten if switching masters
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2 2 2 2 2 2 2 2 2
0 1 2 3 4 5 6 7 8
PARB
2 3 3
9 0 1