Motorola MVME2600 Series Reference Manual page 73

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
2
2-6
Each external request can be individually enabled or disabled using control
bits in the MPC Arbiter Control Register (MARB). Following reset, all
requests will be enabled.
The MPC Arbiter supports optional bus parking in order to reduce
arbitration latency. If bus parking is enabled, then one of two modes may
be selected. The arbiter can be configured to grant the bus to the last
selected master, or it can be configured to grant the bus to one "default"
device. The parking enable, parking mode and default master information
is represented as control bits within the MARB register.
There is a special 'Glance Mode' incorporated into the MPC Arbiter
design. This mode was designed to compensate for an undesirable
characteristic associated with early release Glance look-aside cache chips.
Under certain conditions, the Glance would not maintain single-level
pipelined operation when the Raven was MPC bus master. When Glance
Mode is enabled, the MPC Arbiter tracks address and data tenures and will
grant bus ownership to non-Raven bus masters in a manner that guarantees
single-level pipelined depth. This mode is controlled by the GLMD bit
within the MPC Arbiter Control register. The default state is to have this
mode disabled.
There is another special mode called 'Benign Address Retry Mode'. This
mode was designed to compensate for an anomaly discovered when
running a PPC603 and a pair of early release Falcon memory controllers.
It is possible that contention of the PPC603 single port cache tag memory
causes the PPC603 to issue a false (benign) address retry. Under certain
circumstances, these benign address retry cycles would create problems
with Falcon. When the Benign Address Retry Mode is enabled, the MPC
Arbiter will be watching for benign address retry cycles. When one is
detected, the arbiter will hold-off all non-Raven bus masters for a short
period of time. This mode is controlled by the BAMD bit within the MPC
Arbiter Control register. The default state is to have this mode enabled.
A side benefit of the Benign Address Retry Mode is that it provides a
possible solution to a known live-lock condition that can happen when the
603 is executing a tight loop out of cache and another master is attempting
to transfer a coherent cache line to or from memory. The Benign Address
Retry Mode effectively introduces jitter between the contesting
participants.