Table 3-2. Powerpc 60X Bus To Dram Access Timing When Configured For 60Ns - Motorola MVME2600 Series Reference Manual

Table 3-2. PowerPC 60x Bus to DRAM Access Timing When Configured for
ACCESS TYPE
4-Beat Read after Idle (Quad-word
aligned)
4-Beat Read after Idle (Quad-word
misaligned)
4-Beat Read after 4-Beat Read
(Quad-word aligned)
4-Beat Read after 4-Beat Read
(misaligned)
4-Beat Write after Idle
4-Beat Write after 4-Beat Write
(Quad-word aligned)
1-Beat Read after Idle
1-Beat Read after 1-Beat Read
1-Beat Write after Idle
1-Beat Write after 1-Beat Write
Notes:
1. These numbers assume that the PowerPC 60x bus master is doing
address pipelining with TS_ occurring at the minimum time after
AACK_ is asserted. Also the two numbers shown in the 1st beat
column are for page hit/page miss.
2. In some cases, the numbers shown are averages and specific
instances may be longer or shorter.
60ns Page Devices.
CLOCK PERIODS REQUIRED FOR:
1st 2nd
Beat Beat
9 1
9 3
1
7/3 1
1
6/2 3
4 1
1
7/3 1
9 -
1
9/6 -
-
4
1
-
13/10
Functional Description
Total
3rd 4th
Clocks
Beat Beat
2 1
1 1
2 1 11/7
1 1 11/7
1 1
1 1 10/6
- -
9/6
- -
- -
- - 13/10
3
13
14
7
9
4
3-9