Chip Defaults; External Register Set - Motorola MVME2600 Series Reference Manual

Falcon ECC Memory Controller Chip Set
3

Chip Defaults

External Register Set

3-22
The tester
The refresher/scrubber
The Falcon pair's arbiters assign priority with the refresher/scrubber
highest, the tester next, and the PowerPC 60x bus lowest. When no
requests are pending, the arbiter defaults to providing a PowerPC 60x bus
grant. This provides fast response for PowerPC 60x bus cycles. Although
the arbiter operates on a priority basis, it also performs a pseudo round-
robin algorithm in order to prevent starving any of the requesting entities.
Note that PowerPC DRAM or ROM/Flash accesses should not be
attempted while the tester is in operation.
Some jumper option kinds of parameters need to be configured by
software in the Falcon pair. These parameters include DRAM and
ROM/Flash attributes. In order to set up these parameters correctly,
software needs some way of knowing about the devices that are being used
with the Falcon pair. One way of providing this information is by using the
power-up status registers in the Falcon pair. At power-up reset, each
Falcon latches the level on its RD0-RD63 signal pins into its power-up
status registers. Since the RD signal pins are high impedance during reset,
their power-up reset level can be controlled by pullup/pulldown resistors.
(They are pulled-up internally.)
Each chip in the Falcon pair has an external register chip select pin which
enables it to talk to an external set of registers. This interface is like the
ROM/Flash interface but with less flexibility. It is intended for the system
designer to be able to implement general-purpose status/control signals
with this external set. Refer to the Programming Model in this chapter for
a description of this register set.