Motorola MVME2600 Series Reference Manual page 280

Mvme2600/2700 series single board computer
Hide thumbs Also See for MVME2600 Series:
Table of Contents

Advertisement

I
I/O Base Register
2-46
In-Service Register (ISR)
interpretation of MID3-MID0
Interprocessor Interrupt Dispatch Registers
2-76
interprocessor interrupts
2-81
interprocessor interrupts (IPI)
Interrupt Acknowledge Register
Interrupt Acknowledge Registers
interrupt delivery modes
2-55
Interrupt Enable Control Bits
interrupt handling
5-2
Interrupt Pending Register (IPR)
Interrupt Request Register (IRR)
interrupt router
2-59
interrupt selector (IS)
2-58
interrupt source priority
2-53
Interrupt Task Priority Registers
interrupter
4-6
interrupter and interrupt handler
introduction 2-1, 2-52, 4-1,
IPI Vector/Priority Registers
ISA DMA channels 1-49,
ISA local resource bus
1-34
L
L2 Cache Support
3-13
L2CLM_
3-13
Large Scale Integration (LSI)
little-endian mode
5-13
LM/SIG Control Register
LM/SIG Status Register
1-41
Location Monitor Lower Base Address Reg-
ister
1-43
Location Monitor Upper Base Address Reg-
ister
1-42
M
manual terminology
1-2
manufacturers' documents
mcken
3-40
http://www.mcg.mot.com/literature
Memory Base Register
Memory Configuration Register (MEMCR)
2-59
memory maps
1-48
mien
MK48T59 access registers
module configuration and status registers
2-54
Motorola Computer Group documents
2-82
MPC arbiter
2-78
MPC Arbiter Control Register
MPC bus interface
3-40
MPC bus timer
MPC Error Address Register
2-58
MPC Error Attribute Register - MERAT
2-59
MPC Error Enable Register
MPC Error Status Register
MPC map decoders
MPC master
2-76
MPC registers
MPC Slave Address (0,1 and 2) Registers
4-6
5-1
MPC Slave Address (3) Register
2-68
MPC Slave Offset/Attribute (0,1 and 2) Reg-
5-7
MPC Slave Offset/Attribute (3) Registers
MPC transfer types
MPC write posting
1-1
MPIC registers
MVME2600 series
1-40
MVME2600 series features summary
MVME2600 series interrupt architecture
MVME2600 series system block diagram
MVME712M mode
MVME761 mode
N
negation, definition
nesting of interrupt events
A-5
NVRAM/RTC & Watchdog Timer Registers
2-46
1-30
1-8
3-40
1-35
1-35
2-5
2-28
2-5
2-10
2-34
2-30
2-32
2-7
2-9
2-22
2-37
isters
2-39
2-40
2-10
2-8
2-61
1-2
1-7
1-7
1-2
2-53
1-34
A-1
2-34
2-38
1-4
5-2
1-6
I
N
D
E
X
IN-3

Advertisement

Table of Contents
loading

Table of Contents