Table 5-5. Error Notification And Handling - Motorola MVME2600 Series Reference Manual

Programming Details
Error Notification and Handling
5
Cause
Single-bit ECC
Double-bit ECC
MPC Bus Time Out
PCI Target Abort
PCI Master Abort
PERR# Detected
SERR# Detected
5-10
The Raven and Falcon chipset can detect certain hardware errors and can
be programmed to report these errors via the RavenMPIC interrupts or
Machine Check Interrupt. Note that the TEA* signal is not used at all by
the MVME2600/2700 series. The following table summarizes how the
hardware errors are handled by the MVME2600 series:

Table 5-5. Error Notification and Handling

Store: Write corrected data to memory
Load: Present corrected data to the MPC master
Generate interrupt via RavenMPIC if so enabled
Store: Terminate the bus cycle normally without writing to DRAM
Load: Present un-corrected data to the MPC master
Generate interrupt via RavenMPIC if so enabled
Generate Machine Check Interrupt to the Processor(s) if so enabled
Store: Discard write data and terminate bus cycle normally
Load: Present undefined data to the MPC master
Generate interrupt via RavenMPIC if so enabled
Generate Machine Check Interrupt to the Processor(s) if so enabled
Store: Discard write data and terminate bus cycle normally
Load: Return all 1's and terminate bus cycle normally
Generate interrupt via RavenMPIC if so enabled
Generate Machine Check Interrupt to the Processor(s) if so enabled
Store: Discard write data and terminate bus cycle normally
Load: Return all 1's and terminate bus cycle normally
Generate interrupt via RavenMPIC if so enabled
Generate Machine Check Interrupt to the Processor(s) if so enabled
Generate interrupt via RavenMPIC if so enabled
Generate Machine Check Interrupt to the Processor(s) if so enabled
Generate interrupt via RavenMPIC if so enabled
Generate Machine Check Interrupt to the Processor(s) if so enabled
Action