Interrupt Acknowledge Registers; End-Of-Interrupt Registers - Motorola MVME2600 Series Reference Manual
Mvme2600/2700 series single board computer
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Also See for MVME2600 Series:
- Installation and use manual (198 pages) ,
- Installation and use manual (20 pages) ,
- Programmer's reference manual (20 pages)
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Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
Interrupt Acknowledge Registers
2
Offset
Bit
3
1
Name
Operation
Reset
End-of-Interrupt Registers
Offset
Bit
3
1
Name
Operation
Reset
2-78
3
2
2
2
2
2
2
2
2
2
0
9
8
7
6
5
4
3
2
1
R
$00
On PowerPC-based systems, Interrupt Acknowledge is implemented as a
read request to a memory-mapped Interrupt Acknowledge register.
Reading the Interrupt Acknowledge register returns the interrupt vector
corresponding to the highest priority pending interrupt. Reading this
register also has the following side effects.
The associated bit in the Interrupt Pending Register is cleared.
Reading this register will update the In-Service register.
Reading this register without a pending interrupt will return a value of $FF
hex.
3
2
2
2
2
2
2
2
2
2
0
9
8
7
6
5
4
3
2
1
R
$00
EOI
END OF INTERRUPT. There is one EOI register per
processor. EOI Code values other than 0 are currently
undefined. Data values written to this register are ignored;
zero is assumed. Writing to this register signals the end of
processing for the highest priority interrupt currently in
Processor 0 $200A0
Processor 1 $210A0
2
1
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
2
1
R
R
$00
$00
Processor 0 $200B0
Processor 1 $210B0
2
1
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
2
1
R
R
$00
$00
1
0 9 8 7 6 5 4 3 2 1 0
VECTOR
R
$FF
1
0 9 8 7 6 5 4 3 2 1 0
EOI
R
W
$0
$0
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