Table 3-6. Error Reporting - Motorola MVME2600 Series Reference Manual

Falcon ECC Memory Controller Chip Set
3
Error Type
Terminate the Pow-
erPC 60x bus cycle
normally.
Provide corrected data
Single-Bit
to the PowerPC 60x
Error bus master.
Assert INT_ if so
enabled.
Terminate the Pow-
erPC 60x bus cycle
normally.
Provide miss-cor-
rected, raw DRAM
Double-Bit
data to the PowerPC
Error
60x bus master.
Assert INT_ if so
enabled.
Assert MCP_ if so
enabled.
Some of these errors are detected correctly and are treated the same as double-bit errors. The
Triple- (or
rest could show up as "no error" or "single-bit error", both of which are incorrect.
greater)
Bit Error
3-14
Note that the Falcon pair does not assert TEA_ on double-bit errors. In fact,
the Falcon pair does not have a TEA_ signal pin and it assumes that the
system does not implement TEA_. The Falcon can, however, assert
machine check (MCP_) on double-bit error.

Table 3-6. Error Reporting

Single-Beat/Four-
Single-Beat Write
Beat Read
Terminate the Pow-
erPC 60x bus cycle
normally.
Correct the data read
from DRAM, merge
with the write data, and
write the corrected,
merged data to DRAM.
Assert INT_ if so
enabled.
Terminate the Pow-
erPC 60x bus cycle
normally.
Do not perform the
write portion of the
read-modify-write cycle
to DRAM.
Assert INT_ if so
enabled.
Assert MCP_ if so
enabled.
Notes:
1. No opportunity for error since no read of DRAM occurs during a
four-beat write.
Four-Beat Write
This cycle is not seen
on the PowerPC 60x
bus.
Write corrected data
back to DRAM if so
1
N/A enabled.
Assert INT_ if so
enabled.
This cycle is not seen
on the PowerPC 60x
bus.
Do not perform the
1
N/A write portion of the
read-modify-write
cycle to DRAM.
Assert INT_ if so
enabled.
Scrub