Requirements; Features - Motorola MVME2600 Series Reference Manual

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

Requirements

2

Features

2-2
The Raven must provide a high throughput interface between multiple
MPC60x processors and 32/64-bit PCI local bus. It must be capable of
supporting up to two MPC60x processors and contain a multiprocessing
interrupt structure to efficiently distribute interrupts dynamically between
these processors.
MPC Bus Interface
– Direct interface to MPC601, MPC603 or MPC604 processors.
– 64-bit data bus, 32-bit address bus.
– Optional bus arbitration logic supporting up to three bus masters.
– Four independent software programmable slave map decoders.
– Multi-level write post FIFO for writes to PCI.
– Support for MPC bus clock speeds up to 66 MHz.
– Selectable big or little endian operation.
PCI Interface
– Fully PCI Rev. 2.0 compliant.
– 32-bit or 64-bit address/data bus.
– Support for accesses to all four PCI address spaces.
– Single-level write posting buffers for writes to the MPC bus.
– Read-ahead buffer for reads from the MPC bus.
– Four independent software programmable slave map decoders.
Interrupt Controller
– MPIC compliant.
– Support for 16 external interrupt sources and two processors.
– Multiprocessor interrupt control allowing any interrupt source to
be directed to either processor.
– Multilevel cross processor interrupt control for multiprocessor
synchronization.