System External Cache Control Register (Sxccr) - Motorola MVME2600 Series Reference Manual

R_A/B_TYP[0:1]
ROM_A/B_TYP[0:2]
0b000 to 0b101
Note: The device width is different from the width of the FLASH bank. If
the bank width is 64-bit and the device width is 16-bit then the FLASH
bank consists of four FLASH devices.

System External Cache Control Register (SXCCR)

The System Cache Control Register is accessed via the RD[32:39] data
lines of the upper Falcon device. This 8-bit register is defined as follows:
REG
BIT 0
FIELD
OPER
RESET 1
SXC_DIS_ System External Cache Enable. When this bit is cleared,
These two bits reflect the combined status of the four
blocks of DRAM. Initialization software uses this
information to program the ram_spd0 and ram_spd1
control bits in the Falcon's Chip Revision Register.
ROM/Flash Type. This field is encoded as
follows:
Reserved
Intel 16-bit wide FLASH with 16K Bottom Boot
0b110
Block
0b111 Unknown type (i.e. ROM/FLASH Sockets)
System External Cache Control Register - $FEF88000
1 2 3
1 1 1
it disables this cache from responding to any bus cycles.
Programming Model
ROM/FLASH Type
4 5
R/W
X X
1
6 7
X X
1-31