Isa Local Resource Bus; W83C553 Pib Registers; Pc87308Vul Super I/O (Isasio) Strapping; Nvram/Rtc & Watchdog Timer Registers - Motorola MVME2600 Series Reference Manual

Board Description and Memory Maps
1

ISA Local Resource Bus

W83C553 PIB Registers

PC87308VUL Super I/O (ISASIO) Strapping

Table 1-16. Strap Pins Configuration for the PC87308VUL

Pins
CFG0
CFG1
CFG3, CFG2
BADDR1, BADDR2
SELCS
NVRAM/RTC & Watchdog Timer Registers
1-34
The PIB contains ISA Bridge I/O registers for various functions. These
registers are actually accessible from the PCI bus. Refer to the W83C553
Data Book for details.
The PC87308VUL Super I/O (ISASIO) provides the following functions
to the MVME2600/2700 series: a keyboard interface, a PS/2 mouse
interface, a PS/2 floppy port, two async serial ports and a parallel port.
Refer to the PC87308VUL Data Sheet for additional details and
programming information.
The following table shows the hardware strapping for the Super I/O
device:
0 - FDC, KBC and RTC wake up inactive.
1 - Xbus Data Buffer (XDB) enabled.
00 - Clock source is 24MHz fed via X1 pin.
11 - PnP Motherboard, Wake in Config State. Index $002E.
1 - CS0# on CS0# pin.
The MK48T59/559 provides the MVME2600/2700 series with 8K of non-
volatile SRAM, a time-of-day clock, and a watchdog timer. Accesses to
the MK48T59559 are accomplished via three registers: The
NVRAM/RTC Address Strobe 0 Register, the NVRAM/RTC Address
Reset Configuration