Pci Slave Attribute/ Offset (0,1,2 And 3) Registers - Motorola MVME2600 Series Reference Manual

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
2

PCI Slave Attribute/ Offset (0,1,2 and 3) Registers

Offset
Bit 3
1
Name
Operation
Reset
2-48
START Start Address. This field determines the start address of
a particular memory area on the PCI bus which will be
used to access MPC bus resources. The value of this field
will be compared with the upper 16 bits of the incoming
PCI address.
END End Address. This field determines the end address of a
particular memory area on the PCI bus which will be used
to access MPC bus resources. The value of this field will
be compared with the upper 16 bits of the incoming PCI
address.
3 2 2 2 2 2 2 2 2 2
0 9 8 7 6 5 4 3 2 1
PSOFFx
R/W
$0000
INV Invalidate Enable. If set, the MPC master will issue a
transfer type code which specifies the current transaction
should cause an invalidate for each MPC transaction
originated by the corresponding PCI slave. The transfer
type codes generated are shown in Table 2-3.
GBL Global Enable. If set, the MPC master will assert the
GBL* pin for each MPC transaction originated by the
corresponding PCI slave.
PSATT0/PSOFF0 - $84
PSATT1/PSOFF1 - $8C
PSATT2/PSOFF2 - $94
PSATT3/PSOFF3 - $9C
2 1 1 1 1 1 1 1 1 1
0 9 8 7 6 5 4 3 2 1
R
$00
1
0 9 8 7 6 5 4 3 2 1 0
PSATTx