Table 3-12. Rtest Encodings; Refresh/Scrub Address Register - Motorola MVME2600 Series Reference Manual

Falcon ECC Memory Controller Chip Set
3

Refresh/Scrub Address Register

ADDRESS
BIT
NAME
OPERATIO
N
RESET
3-44
swen When set, swen allows the scrubber to perform write
cycles. When cleared, swen prevents scrubber writes.
rtest0,1,2 The rtest bits enable certain refresh counter test modes.
Table 3-12 shows their encodings. Note that these test
modes are not intended to be used once the chip is in a
system.

Table 3-12. rtest encodings

rtest0,rtest1,rtest2
%000
%001
%010
%011
%100
%101
%110
%111
ROW ADDRESS
READ/WRITE
0 P
ROW ADDRESS
the refresher/scrubber for all blocks of DRAM. The row
address counter increments by one after each
refresh/scrub cycle. When it reaches all 1s, it rolls back
over to all 0s and continues counting. ROW ADDRESS is
readable and writable for test purposes.
Note that within each block, the most significant bits of
ROW ADDRESS are used only when their DRAM
devices are large enough to require them.
Test Mode selected
Normal Counter Operation
RA counts at 16x
RA counts at 256x
RA is always at roll value for CA
CA counts at 16x
CA counts at 256x
reserved
reserved
$FEF80048
These bits form the row address counter used by
COL ADDRESS
READ/WRITE
0 P