Table 3-1. Powerpc 60X Bus To Dram Access Timing When Configured For - Motorola MVME2600 Series Reference Manual

Falcon ECC Memory Controller Chip Set

Table 3-1. PowerPC 60x Bus to DRAM Access Timing When Configured for

3
ACCESS TYPE
4-Beat Read after Idle (Quad-word
aligned)
4-Beat Read after Idle (Quad-word
misaligned)
4-Beat Read after 4-Beat Read
(Quad-word aligned)
4-Beat Read after 4-Beat Read
(misaligned)
4-Beat Write after Idle
4-Beat Write after 4-Beat Write
(Quad-word aligned)
1-Beat Read after Idle
1-Beat Read after 1-Beat Read
1-Beat Write after Idle
1-Beat Write after 1-Beat Write
3-8
70ns Page Devices
CLOCK PERIODS REQUIRED FOR:
Beat
9/3
7/2
10/6
11/7
15/11
Notes:
1. These numbers assume that the PowerPC 60x bus master is doing
address pipelining with TS_ occurring at the minimum time after
AACK_ is asserted. Also the two numbers shown in the 1st beat
column are for page hit/page miss.
2. In some cases, the numbers shown are averages and specific
instances may be longer or shorter.
1st 2nd 3rd
Beat Beat
10 1
10 4
1
1
1
4
4 1
1
1
10 -
1
-
-
4
1
-
Total
4th
Clocks
Beat
3 1 15
1 1 16
3 1 14/8
1 1 13/8
7
1 1
1 1 13/9
10
- -
11/7
- -
4
- -
- - 15/11