I/O Base Register; Memory Base Register - Motorola MVME2600 Series Reference Manual
Mvme2600/2700 series single board computer
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Also See for MVME2600 Series:
- Installation and use manual (198 pages) ,
- Installation and use manual (20 pages) ,
- Programmer's reference manual (20 pages)
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Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
I/O Base Register
2
Offset
Bit
3
1
Name
Operation
Reset
Memory Base Register
Offset
Bit
3
1
Name
Operation
Reset
2-46
3
2
2
2
2
2
2
2
2
2
0
9
8
7
6
5
4
3
2
1
IOBA
R/W
$0000
This register controls the mapping of the MPIC control registers in PCI I/O
space.
IO/MEM IO Space Indicator. This bit is hard-wired to a logic one
to indicate PCI I/O space.
RES
Reserved. This bit is hard-wired to zero.
IOBA
I/O Base Address. These bits define the I/O space base
address of the MPIC control registers. The IOBASE
decoder is disabled when the IOBASE value is zero.
3
2
2
2
2
2
2
2
2
2
0
9
8
7
6
5
4
3
2
1
MEMBA
R/W
$0000
$10
2
1
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
2
1
IOBASE
$14
2
1
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
2
1
MEMBASE
R
$0000
1
0 9 8 7 6 5 4 3 2 1 0
R
$0000
1
0 9 8 7 6 5 4 3 2 1 0
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