Cycles Originating From Pci; Error Handling; Table 2-4. Address Modification For Little Endian Transfers - Motorola MVME2600 Series Reference Manual

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

Table 2-4. Address Modification for Little Endian Transfers

2

Cycles Originating From PCI

Error Handling

2-18
Data Length
(bytes)
1
2
4
8
Note
The only legal data lengths supported in little endian mode
are 1, 2, 4, or 8-byte aligned transfers.
For bus cycles initiated by PCI masters, the PCI address will be modified
the same way the MCP60x processor does in little endian mode. The
modification will be the same as that described in Section 3.7.2 above.
Since this method has some difficulties dealing with unaligned transfers,
the Raven will break up all unaligned PCI transfers into multiple aligned
transfers on the MPC bus.
The Raven will be capable of detecting and reporting the following errors
to one or more MPC masters:
MPC address bus time-out
PCI master signalled master abort
PCI master received target abort
PCI parity error
PCI system error
Address Modification
XOR with 111
XOR with 110
XOR with 100
no change